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1 for more information www.analog.com typical application features description 20 v in , 5 a step - down dc / dc module regulator the lt m ? 4625 is a complete 5 a step-down switching mode module ( micromodule ) regulator in a tiny 6.25 mm 6.25 mm 5.01 mm bga package . included in the pack - age are the switching controller , power fets , inductor and support components . operating over an input voltage range of 4 v to 20 v or 2.375 v to 20 v with an external bias supply , the ltm 4625 supports an output voltage range of 0.6 v to 5.5 v , set by a single external resistor . its high efficiency design delivers up to 5 a continuous output current . only bulk input and output capacitors are needed . the ltm 4625 supports selectable discontinuous mode operation and output voltage tracking for supply rail se - quencing . its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability . fault protection features include overvoltage , overcurrent and overtemperature protection . the ltm 4625 is available with snpb or rohs compliant terminal finish . 5 a , 1.5 v output dc / dc module ? step - down regulator 1.5 v output efficiency vs load current applications n complete solution in <1cm 2 (single-sided pcb) or 0.5cm 2 (dual-sided pcb) n wide input voltage range: 4v to 20v n input voltage down to 2.375v with external bias n 0.6v to 5.5v output voltage n 5a dc output current n 1.5% maximum total dc output voltage error over line, load and temperature n current mode control, fast transient response n external frequency synchronization n multiphase parallel current sharing with multiple?LTM4625s n output voltage tracking n selectable discontinuous mode n power good indicator n overvoltage, overcurrent and overtemperature protection n 6.25mm 6.25mm 5.01mm bga package n telecom, datacom, networking and industrial equipment n medical diagnostic equipment n data storage rack units and cards n test and debug systems all registered trademarks and trademarks are the property of their respective owners . r cc rc r c c c load current (a) 0 efficiency (%) 80 85 90 5 4625 ta01b 75 70 1 2 3 4 60 65 95 v in = 5v v in = 12v document feedback LTM4625 rev c
2 for more information www.analog.com http :// www . linear . com / product / ltm 4625 # orderinfo order information pin configuration absolute maximum ratings v in , sv in .................................................... C0.3 v to 22 v run ........................................................... C0.3 v to 22 v pgood , mode , track / ss , freq , phmode , clkin .................................................... C0.3 v to intv cc internal operating temperature range ( notes 2, 5) ............................................ C40 c to 125 c storage temperature range .................. C55 c to 125 c peak solder reflow body temperature ................. 245 c ( note 1) ( see pin functions , pin configuration table ) c c c c c c c c r r c r r r c cc r rc r c c c electrical characteristics the l denotes the specifications which apply over the specified internal operating temperature range ( note 2), otherwise specifications are at t a = 25 c . v in = sv in = 12 v per the typical application shown on the front page . symbol parameter conditions min typ max units switching regulator section : per channel v in input dc voltage sv in = v in l 4 20 v v out output voltage range l 0.6 5.5 v v out ( dc ) output voltage , total variation with line and load c in = 22 f , c out = 100 f ceramic , r fb = 40.2 k , mode = intv cc , i out = 0 a to 5 a ( note 3) C40 c to 125 c l 1.477 1.50 1.523 v v run run pin on threshold v run rising 1.1 1.2 1.3 v i q ( svin ) input supply bias current v in = 12 v , v out = 1.5 v , mode = intv cc v in = 12 v , v out = 1.5 v , mode = gnd shutdown , run = 0, v in = 12 v 6 2 11 ma ma a i s ( vin ) input supply current v in = 12 v , v out = 1.5 v , i out = 5 a 0.75 a part number pad or ball finish part marking * package type msl rating temperature range ( note 2) device finish code ltm 4625 ey # pbf sac 305 ( rohs ) ltm 4625 y e 1 bga 3 C40 c to 125 c ltm 4625 iy # pbf sac 305 ( rohs ) ltm 4625 y e 1 bga 3 C40 c to 125 c ltm 4625 iy snpb (63/37) ltm 4625 y e 0 bga 3 C40 c to 125 c consult marketing for parts specified with wider operating temperature ranges . * device temperature grade is indicated by a label on the shipping container . pad or ball finish code is per ipc / jedec j-std- 609. ? terminal finish part marking : www . linear . com / leadfree ? recommended lga and bga pcb assembly and manufacturing procedures : www . linear . com / umodule / pcbassembly ? lga and bga package and tray drawings : www . linear . com / packaging LTM4625 rev c
3 for more information www.analog.com electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device . exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime . note 2: the ltm 4625 is tested under pulsed load conditions such that t j t a . the ltm 4625 e is guaranteed to meet performance specifications over the 0 c to 125 c internal operating temperature range . specifications over the C40 c to 125 c internal operating temperature range are assured by design , characterization and correlation with statistical process controls . the ltm 4625 i is guaranteed to meet specifications over the full C40 c to 125 c internal operating temperature range . note that the symbol parameter conditions min typ max units i out ( dc ) output continuous current range v in = 12 v , v out = 1.5 v 0 5 a v out ( line )/ v out line regulation accuracy v out = 1.5 v , v in = 4 v to 20 v , i out = 0 a l 0.04 0.15 %/ v v out ( load )/ v out load regulation accuracy v out = 1.5 v , i out = 0 a to 5 a l 0.5 1.5 % v out ( ac ) output ripple voltage i out = 0 a , c out = 100 f ceramic , v in = 12 v , v out = 1.5 v 5 mv v out ( start ) turn-on overshoot i out = 0 a , c out = 100 f ceramic , v in = 12 v , v out = 1.5 v 30 mv t start turn-on time c out = 100 f ceramic , no load , track / ss = 0.01 f , v in = 12 v , v out = 1.5 v 2.5 ms v outls peak deviation for dynamic load load : 0% to 50% to 0% of full load , c out = 47 f ceramic , v in = 12 v , v out = 1.5 v 160 mv t settle settling time for dynamic load step load : 0% to 50% to 0% of full load , c out = 47 f ceramic , v in = 12 v , v out = 1.5 v 40 s i outpk output current limit v in = 12 v , v out = 1.5 v 6 7 a v fb voltage at fb pin i out = 0 a , v out = 1.5 v , C40 c to 125 c l 0.593 0.60 0.607 v i fb current at fb pin ( note 4) 30 na r fbhi resistor between v out and fb pins 60.05 60.40 60.75 k i track / ss track pin soft-start pull-up current track / ss = 0 v 2.0 4 a v in ( uvlo ) v in undervoltage lockout v in falling v in hysteresis 2.4 2.6 350 2.8 v mv t on ( min ) minimum on-time ( note 4) 40 ns t off ( min ) minimum off-time ( note 4) 70 ns v pgood pgood trip level v fb with respect to set output v fb ramping negative v fb ramping positive C15 7 C10 10 C7 15 % % i pgood pgood leakage 2 a v pgl pgood voltage low i pgood = 1 ma 0.02 0.1 v v intvcc internal v cc voltage sv in = 4 v to 20 v 3.1 3.2 3.3 v f osc oscillator frequency 1 mhz maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout , the rated package thermal resistance and other environmental factors . note 3: see output current derating curves for different v in , v out and t a . note 4: 100% tested at wafer level . note 5: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions . junction temperature will exceed 125 c when overtemperature protection is active . continuous operation above the specified maximum operating junction temperature may impair device reliability . the l denotes the specifications which apply over the specified internal operating temperature range ( note 2), otherwise specifications are at t a = 25 c . v in = sv in = 12 v per the typical application shown on the front page . LTM4625 rev c
4 for more information www.analog.com typical performance characteristics 1 v output transient response 3.3 v output transient response 1.5 v output transient response 5 v output transient response 2.5 v output transient response efficiency vs load current from 5 v in efficiency vs load current from 12 v in dcm mode efficiency , v out = 1.5 v load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 10 4625 g03 0 0.01 v in = 5v v in = 12v v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1v i out = 4a to 5a, 1a/s output capacitor = 47f ceramic 20s/div 4625 g04 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 1.5v i out = 4a to 5a, 1a/s output capacitor = 47f ceramic 20s/div 4625 g05 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 2.5v i out = 4a to 5a, 1a/s output capacitor = 47f ceramic 20s/div 4625 g06 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 3.3v i out = 4a to 5a, 1a/s output capacitor = 47f ceramic 20s/div 4625 g07 v out 50mv/div ac-coupled load step 1a/div v in = 12v v out = 5v i out = 4a to 5a, 1a/s output capacitor = 47f ceramic 20s/div 4625 g08 load current (a) 0 efficiency (%) 80 85 90 5 4625 g01 75 70 1 2 3 4 65 100 95 2.5v out 1.5v out 1v out 3.3v out 1.8v out 1.2v out load current (a) 0 efficiency (%) 80 85 90 5 4625 g02 75 70 1 2 3 4 60 65 95 3.3v out 1.8v out 1.2v out 5v out 2.5v out 1.5v out 1v out LTM4625 rev c
5 for more information www.analog.com start-up with no load current short-circuit with no load applied start-up with 5 a load current short-circuit with 5 a load applied steady-state output voltage ripple recovery from short-circuit with no load applied start into pre-biased output typical performance characteristics v out 0.5v/div i in 2a/div 5ms/div v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor soft-start capacitor = 0.1f 4625 g09 v out 0.5v/div i in 2a/div v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor soft-start capacitor = 0.1f 4625 g10 5ms/div i in 500ma/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 4625 g11 20s/div i in 500ma/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 50s/div 4625 g12 v out 5mv/div ac-coupled v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 20mhz bw 4625 g14 1s/div i in 1a/div v out 0.5v/div v in = 12v v out = 1.5v input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 4625 g13 20s/div v in 5v/div v out 0.5v/div v in = 12v v out = 1.5v with 0.75v prebiased voltage input capacitor = 22f sanyo electrolytic capacitor + 22f ceramic capacitor output capacitor = 47f ceramic capacitor 4625 g15 5ms/div LTM4625 rev c
6 for more information www.analog.com pin functions comp ( a 1): current control threshold and error ampli - fier compensation point . the current comparator s trip threshold is linearly proportional to this voltage , whose normal range is from 0.3 v to 1.8 v . tie the comp pins together for parallel operation . the device is internally compensated . strictly an output pin . do not drive this pin . track / ss ( a 2): output tracking and soft-start input . allows the user to control the rise time of the output volt - age . putting a voltage below 0.6 v on this pin bypasses the internal reference input to the error amplifier , and servos the fb pin to match the track / ss voltage . above 0.6 v , the tracking function stops and the internal reference resumes control of the error amplifier . there s an internal 2 a pull-up current from intv cc on this pin , so putting a capacitor here provides a soft-start function . run ( a 3): run control input of the switching mode regulator . enables chip operation by tying run above 1.2 v . pulling it below 1.1 v shuts down the part . do not leave floating . freq ( a 4): frequency is set internally to 1 mhz . an ex - ternal resistor can be placed from this pin to sgnd to increase frequency , or from this pin to intv cc to reduce frequency . see the applications information section for frequency adjustment . fb ( b 1): the negative input of the error amplifier . inter - nally , this pin is connected to v out with a 60.4 k precision resistor . different output voltages can be programmed with an additional resistor between the fb and sgnd pins . tying the fb pins together allows for parallel operation . see the applications information for details . phmode ( b 2): control input to phase selector of the switching mode regulator channel . this pin determines the phase relationship between internal oscillator and clkout signal . tie it to intv cc for 2 -phase operation , tie it to sgnd for 3 -phase operation , and tie it to intv cc /2 for 4 -phase operation . gnd ( b 3, c 3, d 3 -d 4, e 3): power ground pins for both input and output returns . sgnd ( b 4): signal ground connection . tie to gnd with minimum distance . connect freq resistor , comp com - ponent , mode , track / ss component , fb resistor to this pin as needed . v out ( c 1, d 1 -d 2, e 1 -e 2): power output pins . apply out - put load between these pins and gnd pins . recommend placing output decoupling capacitance directly between these pins and gnd pins . pgood ( c 2): output power good with open-drain logic . pgood is pulled to ground when the voltage on the fb pin is not within 10% of the internal 0.6 v reference . mode ( c 4): operation mode select . tie this pin to intv cc to force continuous synchronous operation at all output loads . tying it to sgnd enables discontinuous mode operation at light loads . do not leave floating . sv in ( c 5): signal v in . filtered input voltage to the on-chip 3.3 v regulator . tie this pin to the v in pin in most applica - tions or connect sv in to an external voltage supply of at least 4 v which must also be greater than v out . v in ( d 5, e 5): power input pins . apply input voltage be- tween these pins and gnd pins . recommend placing input decoupling capacitance directly between v in pins and gnd pins . intv cc ( e 4): internal regulator output . the internal power drivers and control circuits are powered from this voltage . this pin is internally decoupled to gnd with a 1 f low esr ceramic capacitor . do not drive this pin . clkin ( a 5): external synchronization input to phase detector of the switching mode regulator . this pin is internally terminated to sgnd with 20 k . the phase-locked loop will force the top power nmos s turn-on signal to be synchronized with the rising edge of the clkin signal . clkout ( b 5): output clock signal for polyphase operation of the switching mode regulator . the phase of clkout with respect to clkin is determined by the state of the phmode pin . clkout s peak-to-peak amplitude is intv cc to gnd . do not drive this pin . package row and column labeling may vary among module products . review each package layout carefully . LTM4625 rev c
7 for more information www.analog.com block diagram decoupling requirements symbol parameter conditions min typ max units c in external input capacitor requirement ( v in = 4 v to 20 v , v out = 1.5 v ) i out = 5 a 4.7 10 f c out external output capacitor requirement ( v in = 4 v to 20 v , v out = 1.5 v ) i out = 5 a 22* 47* f * additional capacitance may be required under extreme temperature and / or capacitor bias voltage conditions due to variation of actual capacitance over bias voltage and temperature . figure 1. simplified ltm 4625 block diagram power control fb 60.4k 1f 20k 0.1f r fb 40.2k 0.1f c in 10f 25v intv cc v out mode track/ss run v in clkin clkout phmode comp 1f v out v in sv in 10k pgood v out 1.5v 5a v in 4v to 20v intv cc gnd 1h 4625 bd freq 162k internal comp sgnd internal filter c out 47f 6.3v LTM4625 rev c
8 for more information www.analog.com operation the ltm 4625 is a standalone nonisolated switch mode dc / dc power supply . it can deliver up to 5 a dc output current with few external input and output capacitors . this module provides precisely regulated output voltage adjustable between 0.6 v to 5.5 v via one external resistor over a 4 v to 20 v input voltage range . with an external bias supply above 4 v connected to sv in , this module operates with an input voltage down to 2.375 v . the typical application schematic is shown in figure 20 . the ltm 4625 contains an integrated constant on-time valley current mode regulator , power mosfets , inductor , and other supporting discrete components . the default switching frequency is 1 mhz . for switching noise-sensitive applications , the switching frequency can be adjusted by external resistors and the module regulator can be externally synchronized to a clock within 30% of the set frequency . see the applications information section . with current mode control and internal feedback loop compensation , the ltm 4625 module has sufficient stabil - ity margins and good transient performance with a wide range of output capacitors , even with all ceramic output capacitors . current mode control provides cycle-by-cycle fast cur - rent limiting . foldback current limiting is provided in an overcurrent condition indicated by a drop in v fb reducing inductor valley current to approximately 40% of the origi - nal value . internal output overvoltage and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point . continuous operation is forced during ov and uv condition except during start-up when the track pin is ramping up to 0.6 v . furthermore , in order to protect the internal power mosfet devices against transient voltage spikes , the ltm 4625 constantly monitors the v in pin for an overvoltage condi - tion . when v in rises above 23.5 v , the regulator suspends operation by shutting off both power mosfets . once v in drops below 21.5 v , the regulator immediately resumes normal operation . the regulator does not execute its soft-start function when exiting an overvoltage condition . multiphase operation can be easily employed with the synchronization and phase mode controls . up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the phmode pin to different levels . the ltm 4625 has clkin and clkout pins for polyphase operation of multiple devices or frequency synchronization . pulling the run pin below 1.1 v forces the controller into its shutdown state , turning off both power mosfets and most of the internal control circuitry . at light load currents , discontinuous mode ( dcm ) operation can be enabled to achieve higher efficiency compared to continu - ous mode ( ccm ) by pulling the mode pin to sgnd . the track / ss pin is used for power supply tracking and soft-start programming . see the applications informa - tion section . LTM4625 rev c
9 for more information www.analog.com applications information the typical ltm 4625 application circuit is shown in figure 20 . external component selection is primarily determined by the input voltage , the output voltage and the maximum load current . refer to table 7 for specific external capacitor requirements for a particular application . v in to v out step-down ratios there are restrictions in the maximum v in and v out step - down ratios that can be achieved for a given input voltage due to the minimum off-time and minimum on-time limits of the regulator . the minimum off-time limit imposes a maximum duty cycle which can be calculated as : d max = 1 C ( t off ( min ) ? f sw ) where t off ( min ) is the minimum off-time , typically 70 ns for ltm 4625 , and f sw ( hz ) is the switching frequency . conversely the minimum on-time limit imposes a minimum duty cycle of the converter which can be calculated as : d min = t on ( min ) ? f sw where t on ( min ) is the minimum on-time , typically 40 ns for ltm 4625 . in the rare cases where the minimum duty cycle is surpassed , the output voltage will still remain in regulation , but the switching frequency will decrease from its programmed value . note that additional thermal derating may be applied . see the thermal considerations and output current derating section in this data sheet . output voltage programming the pwm controller has an internal 0.6 v reference voltage . as shown in the block diagram , a 60.4 k internal feedback resistor connects the v out and fb pins together . adding a resistor , r fb , from fb pin to sgnd programs the output voltage : r f b = 0 . 6 v v o u t C 0 . 6 v ? 6 0 . 4 k table 3. r fb resistor table vs various output voltages v out ( v ) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0 r fb ( k ) open 90.9 60.4 40.2 30.1 19.1 13.3 8.25 for parallel operation of n channels , use the following equation to solve for r fb . tie the v out , the comp and fb pins together for each paralleled output . connect a single resistor from fb to gnd as determined by : r f b = 0 . 6 v v o u t C 0 . 6 v ? 6 0 . 4 k n see figure 23 for an example of parallel operation . input decoupling capacitors the ltm 4625 module should be connected to a low ac impedance dc source . for the regulator , a 10 f input ceramic capacitor is required for rms ripple current de - coupling . bulk input capacitance is only needed when the input source impedance is compromised by long inductive leads , traces or not enough source capacitance . the bulk capacitor can be an aluminum electrolytic capacitor or polymer capacitor . without considering the inductor ripple current , the rms current of the input capacitor can be estimated as : i c i n ( r m s ) = i o u t ( m a x ) % ? d ? 1 C d ( ) where % is the estimated efficiency of the power module . output decoupling capacitors with an optimized high frequency , high bandwidth design , only a single low esr output ceramic capacitor is required for the ltm 4625 to achieve low output ripple voltage and very good transient response . in extreme cold or hot tem - perature or high output voltage case , additional ceramic capacitor or tantalum-polymer capacitor is required due to variation of actual capacitance over bias voltage and temperature . table 7 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 1 a or 2 a load-step tran - sient . additional output filtering may be required by the system designer if further reduction of output ripple or dynamic ? transient spikes is required . the analog devices ltpowercad ? design tool is available to download online for output ripple , stability and transient response analysis for further optimization . LTM4625 rev c
10 for more information www.analog.com applications information discontinuous current mode ( dcm ) in applications where low output ripple and high efficiency at intermediate current are desired , discontinuous current mode ( dcm ) should be used by connecting the mode pin to sgnd . at light loads the internal current comparator may remain tripped for several cycles and force the top mosfet to stay off for several cycles , thus skipping cycles . the inductor current does not reverse in this mode . forced continuous current mode ( ccm ) in applications where fixed frequency operation is more critical than low current efficiency , and where the lowest output ripple is desired , forced continuous operation should be used . forced continuous operation can be enabled by tying the mode pin to intv cc . in this mode , inductor current is allowed to reverse during low output loads , the comp voltage is in control of the current comparator threshold throughout , and the top mosfet always turns on with each oscillator pulse . during start-up , forced continuous mode is disabled and inductor current is prevented from revers - ing until the ltm 4625 s output voltage is in regulation . operating frequency the operating frequency of the ltm 4625 is optimized to achieve the compact package size and the minimum out- put ripple voltage while still keeping high efficiency . the default operating frequency is 1 mhz . in most applications , no additional frequency adjustment is required . if an operating frequency other than 1 mhz is required by the application , the operating frequency can be increased by adding a resistor , r fset , between the freq pin and sgnd , as shown in figure 22 . the operating frequency can be calculated as : f h z ( ) = 1 . 6 e 1 1 1 6 2 k | | r f s e t ? ( ) the operating frequency can also be decreased by adding a resistor between the freq pin and intv cc , calculated as : f h z ( ) = 1 m h z C 2 . 8 e 1 1 r f s e t ? ( ) the programmable operating frequency range is from 800 khz to 4 mhz . frequency synchronization and clock in the power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector . this allows the internal top mosfet turn-on to be locked to the rising edge of the external clock . the external clock frequency range must be within 30% around the resistor set operating frequency . a pulse detection circuit is used to detect a clock on the clkin pin to turn on the phase-locked loop . the pulse width of the clock has to be at least 100 ns . the clock high level must be above 2 v and clock low level below 0.3 v . during the start-up of the regulator , the phase-locked loop function is disabled . multiphase operation for output loads that demand more than 5 a of current , multiple ltm 4625 s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples . the clkout signal can be connected to the clkin pin of the following ltm 4625 stage to line up both the frequency and the phase of the entire system . tying the phmode pin to intv cc , sgnd or intv cc /2 generates a phase differ - ence ( between clkin and clkout ) of 180, 120, or 90 respectively , which corresponds to 2 -phase , 3 -phase or 4 -phase operation . a total of 12 phases can be cascaded to run simultaneously out of phase with respect to each other by programming the phmode pin of each ltm 4625 to different levels . figure 2 shows a 4 -phase design and a 6 -phase design example for clock phasing . table 4. phmode pin status and corresponding phase relationship ( relative to clkin ) phmode intv cc sgnd intv cc /2 clkout 180 120 90 a multiphase power supply significantly reduces the amount of ripple current in both the input and output ca - pacitors . the rms input ripple current is reduced by , and the effective ripple frequency is multiplied by , the number LTM4625 rev c
11 for more information www.analog.com of phases used ( assuming that the input voltage is greater than the number of phases used times the output voltage ). the output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design . the ltm 4625 device is an inherently current mode con - trolled device , so parallel modules will have very good current sharing . this will balance the thermals on the design . please tie the run , track / ss , fb and comp pins of each paralleling channel together . figure 23 shows an example of parallel operation and pin connection . input rms ripple current cancellation application note 77 provides a detailed explanation of multiphase operation . the input rms ripple current can - cellation mathematical derivations are presented , and a graph is displayed representing the rms ripple current reduction as a function of the number of interleaved phases . figure 3 shows this graph . applications information figure 2. 4- phase , 6- phase operation figure 3. rms input ripple current to dc load current ratio as a function of duty cycle 4625 f02 clkin phmode clkout 0 90 180 270 +90 +90 +90 phase 4 phase 3 phase 2 phase 1 clkin phmode clkout clkin phmode clkout clkin phmode clkout clkin phmode clkout 120 240 (420) 60 180 +120 +180 +120 phase 4 intv cc intv cc phase 2 phase 5 phase 3 clkin phmode clkout clkin phmode clkout clkin phmode clkout 300 +120 phase 6 clkin phmode clkout 0 phase 1 clkin phmode clkout +120 0.75 0.8 4625 f03 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.85 0.9 duty cycle (v out /v in ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1 phase 2 phase 3 phase 4 phase 6 phase LTM4625 rev c
12 for more information www.analog.com applications information soft-start and output voltage tracking the track / ss pin provides a means to either soft start the regulator or track it to a different power supply . a capacitor on the track / ss pin will program the ramp rate of the output voltage . an internal 2 a current source will charge up the external soft-start capacitor towards intv cc voltage . when the track / ss voltage is below 0.6 v , it will take over the internal 0.6 v reference voltage to control the output voltage . the total soft-start time can be calculated as : t s s = 0 . 6 ? c s s 2 a where c ss is the capacitance on the track / ss pin . cur- rent foldback and forced continuous mode are disabled during the soft-start process . output voltage tracking can also be programmed externally using the track / ss pin . the output can be tracked up and down with another regulator . figure 4 and figure 5 show an example waveform and schematic of ratiometric tracking where the slave regulator s output slew rate is proportional to the master s . since the slave regulator s track / ss is connected to the master s output through a r tr ( top ) / r tr ( bot ) resistor divider and its voltage used to regulate the slave output voltage when track / ss voltage is below 0.6 v , the slave output voltage and the master output voltage should satisfy the following equation during start-up : v o u t ( s l ) ? r f b ( s l ) r f b ( s l ) + 6 0 . 4 k = v o u t ( m a ) ? r t r ( b o t ) r t r ( t o p ) + r t r ( b o t ) figure 4. output ratiometric tracking waveform figure 5. example schematic of ratiometric output voltage tracking time slave output master output output voltage 4625 f04 freq v in sv in run intv cc mode track/ss pgood v out fb comp gnd sgnd r fb(ma) 40.2k LTM4625 10f 25v v in 4v to 20v v out(ma) 1.5v 5a 47f 6.3v r tr(bot) 40.2k r fb(sl) 60.4k r tr(top) 60.4k freq v in sv in run intv cc mode track/ss pgood v out fb comp gnd sgnd 4625 f05 LTM4625 10f 25v v out(sl) 1.2v 5a 47f 6.3v LTM4625 rev c
13 for more information www.analog.com applications information the r fb ( sl ) is the feedback resistor and the r tr ( top ) / r tr ( bot ) is the resistor divider on the track / ss pin of the slave regulator , as shown in figure 5 . following the previous equation , the ratio of the master s output slew rate ( mr ) to the slave s output slew rate ( sr ) is determined by : m r s r = r f b ( s l ) r f b ( s l ) + 6 0 . 4 k r t r ( b o t ) r t r ( t o p ) + r t r ( b o t ) for example , v out ( ma ) =1.5 v , mr = 1.5 v /1 ms and v out ( sl ) = 1.2 v , sr = 1.2 v /1 ms . from the equation , we could solve that r tr ( top ) = 60.4 k and r tr ( bot ) = 40.2 k are a good combination for the ratiometric tracking . the track / ss pin will have the 2 a current source on when a resistive divider is used to implement tracking on the slave regulator . this will impose an offset on the track / ss pin input . smaller value resistors with the same ratios as the resistor values calculated from the above equation can be used . for example , where the 60.4 k is used then a 6.04 k can be used to reduce the track / ss pin offset to a negligible value . coincident output tracking can be recognized as a special ratiometric output tracking in which the master s output slew rate ( mr ) is the same as the slave s output slew rate ( sr ), waveform as shown in figure 6 . from the equation , we could easily find that , in coincident tracking , the slave regulator s track / ss pin resistor divider is always the same as its feedback divider : r f b ( s l ) r f b ( s l ) + 6 0 . 4 k = r t r ( b o t ) r t r ( t o p ) + r t r ( b o t ) for example , r tr ( top ) = 60.4 k and r tr ( bot ) = 60.4 k is a good combination for coincident tracking for a v out ( ma ) = 1.5 v and v out ( sl ) = 1.2 v application . figure 6. output coincident tracking waveform power good the pgood pin is an open-drain pin that can be used to monitor valid output voltage regulation . this pin is pulled low when the output voltage exceeds a 10% window around the regulation point . to prevent unwanted pgood glitches during transients or dynamic v out changes , the ltm 4625 s pgood falling edge includes a blanking delay of approximately 52 switching cycles . stability compensation the ltm 4625 s internal compensation loop is designed and optimized for use with low esr ceramic output capacitors . table 7 is provided for most application requirements . in case a bulk output capacitor is required for output ripple or dynamic transient spike reduction , an additional 10 pf to 15 pf feedforward capacitor ( c ff ) is needed between the v out and fb pins . the ltpowercad design tool is available for control loop optimization . run enable pulling the run pin to ground forces the ltm 4625 into its shutdown state , turning off both power mosfets and most of its internal control circuitry . bringing the run pin above 0.7 v turns on the internal reference only , while still keeping the power mosfets off . increasing the run pin voltage above 1.2 v will turn on the entire chip . time master output slave output output voltage 4625 f06 LTM4625 rev c
14 for more information www.analog.com applications information pre-biased output start-up there may be situations that require the power supply to start up with some charge on the output capacitors . the ltm 4625 can safely power up into a pre-biased output without discharging it . the ltm 4625 accomplishes this by forcing discontinuous mode ( dcm ) operation until the track / ss pin voltage reaches 0.6 v reference voltage . this will prevent the bg from turning on during the pre-biased output start-up which would discharge the output . do not pre-bias ltm 4625 with an output voltage higher than intv cc (3.3 v ) or a voltage higher than the output voltage set by feedback resistor ( r fb ). overtemperature protection the internal overtemperature protection monitors the junc - tion temperature of the module . if the junction temperature reaches approximately 160 c , both power switches will be turned off until the temperature drops about 15 c cooler . low input application the ltm 4625 module has a separate sv in pin which makes it suitable for low input voltage applications down to 2.375 v . the sv in pin is the single input of the whole control circuitry while the v in pin is the power input which directly connects to the drain of the top mosfet . in most applications where v in is greater than 4 v , connect sv in directly to v in with a short trace . an optional filter , con - sisting of a resistor (1 to 10) between sv in and v in along with a 0.1 f bypass capacitor between sv in and ground , can be placed for additional noise immunity . this filter is not necessary in most cases if good pcb layout practices are followed ( see figure 19 ). in a low input voltage (2.375 v to 4 v ) application , or to reduce power dissipation by the internal bias ldo , connect sv in to an external voltage higher than 4 v with a 1 f local bypass capacitor . figure 21 shows an example of a low input voltage application . please note the sv in voltage cannot go below the v out voltage . thermal considerations and output current derating the thermal resistances reported in the pin configuration section of the data sheet are consistent with those param - eters defined by jesd 51 - 12 and are intended for use with finite element analysis ( fea ) software modeling tools that leverage the outcome of thermal modeling , simulation , and correlation to hardware evaluation performed on a module package mounted to a hardware test board . the motivation for providing these thermal coefficients is found in jesd 51 - 12 ( guidelines for reporting and using electronic package thermal information ). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the module regulator s thermal performance in their ap - plication at various electrical and environmental operating conditions to compliment any fea activities . without fea software , the thermal resistances reported in the pin con - figuration section are , in and of themselves , not relevant to providing guidance of thermal performance ; instead , the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one s application usage , and can be adapted to correlate thermal performance to one s own application . the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd 51 - 12; these coefficients are quoted or paraphrased below : 1. ja , the thermal resistance from junction to ambient , is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure . this environment is sometimes referred to as still air although natural convection causes the air to move . this value is determined with the part mounted to a 95 mm 76 mm pcb with four layers . 2. jcbottom , the thermal resistance from junction to the bottom of the product case , is determined with all of the component power dissipation flowing through the bottom of the package . in the typical module regulator , the bulk of the heat flows out the bottom of the pack - age , but there is always heat flow out into the ambient environment . as a result , this thermal resistance value LTM4625 rev c
15 for more information www.analog.com applications information may be useful for comparing packages , but the test conditions don t generally match the user s application . 3. jctop , the thermal resistance from junction to top of the product case , is determined with nearly all of the component power dissipation flowing through the top of the package . as the electrical connections of the typical module regulator are on the bottom of the package , it is rare for an application to operate such that most of the heat flows from the junction to the top of the part . as in the case of jcbottom , this value may be useful for comparing packages but the test conditions don t generally match the user s application . 4. jb , the thermal resistance from junction to the printed circuit board , is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the module package and into the board , and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board . the board temperature is measured a specified distance from the package . a graphical representation of the aforementioned ther - mal resistances is given in figure 7 ; blue resistances are contained within the module regulator , whereas green resistances are external to the module package . as a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by jesd 51 - 12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator . for example , in normal board-mounted applications , never does 100% of the device s total power loss ( heat ) thermally conduct exclusively through the top or exclusively through bot - tom of the module package as the standard defines for jctop and jcbottom , respectively . in practice , power loss is thermally dissipated in both directions away from the package granted , in the absence of a heat sink and airflow , a majority of the heat flow is into the board . within the ltm 4625 be aware there are multiple power devices and components dissipating power , with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss . to reconcile this complication without sacrificing modeling simplicity but also , not ignoring practical realities an approach has been taken using fea software modeling along with laboratory testing in a controlled environment chamber to reason - ably define and correlate the thermal resistance values supplied in this data sheet : (1) initially , fea software is used to accurately build the mechanical geometry of the figure 7. graphical representation of jesd 51-12 thermal coefficients 4625 f07 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance LTM4625 rev c
16 for more information www.analog.com applications information ltm 4625 and the specified pcb with all of the correct material coefficients along with accurate power loss source definitions ; (2) this model simulates a software-defined jedec environment consistent with jsed 51 - 12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the ltm 4625 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model , a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated . an outcome of this process and due diligence yields the set of derating curves shown in this data sheet . after these laboratory tests have been performed and correlated to the ltm 4625 model , then the jb and ba are summed together to provide a value that should closely equal the ja value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink . the 1.0 v , 1.5 v , 3.3 v and 5 v power loss curves in figure 8 to figure 11 can be used in coordination with the load current derating curves in figure 12 to figure 18 for calculating an approximate ja thermal resistance for the ltm 4625 with various airflow conditions . the power loss curves are taken at room temperature , and are increased with a multiplicative factor according to the ambient tempera - ture . this approximate factor is : 1.4 for 120 c at junction temperature . maximum load current is achievable while increasing ambient temperature as long as the junction temperature is less than 120 c , which is a 5 c guard band from maximum junction temperature of 125 c . when the ambient temperature reaches a point where the junction temperature is 120 c , then the load current is lowered to maintain the junction at 120 c while increasing ambient temperature up to 120 c . the derating curves are plotted with the output current starting at 5 a and the ambient tem - perature at 30 c . the output voltages are 1.0 v , 1.5 v , 3.3 v and 5 v . these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance . thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis . the junction temperatures are monitored while ambient temperature is increased with and without airflow . the power loss increase with ambient temperature change is factored into the derating curves . the junctions are maintained at 120 c maximum while lowering output current or power with increasing ambient temperature . the decreased output current will decrease the internal module loss as ambient temperature is increased . the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much module temperature rise can be allowed . as an example , in figure 13 the load current is derated to ~3 a at ~95 c with no air flow or heat sink and the power loss for the 12 v to 1.0 v at 3 a output is about 1.15 w . the 1.15 w loss is calculated with the ~0.82 w room temperature loss from the 12 v to 1.0 v power loss curve at 3 a , and the 1.4 multiplying factor at 120 c junction temperature . if the 95 c ambient temperature is subtracted from the 120 c junction temperature , then the difference of 25 c divided by 1.15 w equals a 22 c / w ja thermal resistance . table 3 specifies a 22 c / w value which is very close . table 4 , table 5 and table 6 provide equivalent thermal resistances for 1.5 v 3.3 v and 5 v outputs with and without airflow and heat sinking . the derived thermal resistances in table 3 , table 4 , table 5 and table 6 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient , thus maximum junction temperature . room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with the above ambient temperature multipli - cative factors . the printed circuit board is a 1.6 mm thick 4 -layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers . the pcb dimensions are 95 mm 76 mm . LTM4625 rev c
17 for more information www.analog.com figure 8. power loss at 1 v output figure 9. power loss at 1.5 v output figure 10. power loss at 3.3 v output applications information figure 11. power loss at 5 v output figure 14. 5 v to 1.5 v derating curve , no heat sink figure 12. 5 v to 1 v derating curve , no heat sink figure 13. 12 v to 1 v derating curve , no heat sink figure 15. 12 v to 1.5 v derating curve , no heat sink load current (a) 0 2.5 3.0 4 4625 f08 2.0 1.5 1 2 3 5 1.0 0.5 0 power loss (w) v in = 5v v in = 12v load current (a) 0 power loss (w) 1.5 2.0 3 5 4645 f09 1.0 0.5 0 1 2 4 2.5 3.0 v in = 5v v in = 12v load current (a) 0 0 power loss (w) 0.5 1.0 2 4 5 3.0 4645 f10 1 3 1.5 2.0 2.5 v in = 5v v in = 12v load current (a) 0 0 power loss (w) 0.5 1.0 2 4 5 3.0 4645 f11 1 3 1.5 2.0 2.5 v in = 12v ambient temperature (c) 30 0 load current (a) 2 1 3 4 90 100 110 120 6 4645 f12 40 50 60 70 80 5 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 1 2 3 90 100 110 6 4645 f13 40 50 60 70 80 120 4 5 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 1 2 3 90 100 110 6 4645 f15 40 50 60 70 80 120 4 5 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 1 2 3 90 100 110 6 4645 f14 40 50 60 70 80 120 4 5 400lfm 200lfm 0lfm LTM4625 rev c
18 for more information www.analog.com applications information figure 17. 12 v to 3.3 v derating curve , no heat sink figure 18. 12 v to 5 v derating curve , no heat sink figure 16. 5 v to 3.3 v derating curve , no heat sink table 3. 1.0 v output derating curve v in ( v ) power loss curve air flow ( lfm ) heat sink ja ( c / w ) figures 12, 13 5, 12 figure 8 0 none 22 figures 12, 13 5, 12 figure 8 200 none 19 figures 12, 13 5, 12 figure 8 400 none 18 table 4. 1.5 v output derating curve v in ( v ) power loss curve air flow ( lfm ) heat sink ja ( c / w ) figures 14, 15 5, 12 figure 9 0 none 22 figures 14, 15 5, 12 figure 9 200 none 19 figures 14, 15 5, 12 figure 9 400 none 18 table 5. 3.3 v output derating curve v in ( v ) power loss curve air flow ( lfm ) heat sink ja ( c / w ) figures 16, 17 5, 12 figure 10 0 none 22 figures 16, 17 5, 12 figure 10 200 none 19 figures 16, 17 5, 12 figure 10 400 none 18 table 6. 5 v output derating curve v in ( v ) power loss curve air flow ( lfm ) heat sink ja ( c / w ) figure 18 12 figure 11 0 none 22 figure 18 12 figure 11 200 none 19 figure 18 12 figure 11 400 none 18 ambient temperature (c) 30 0 load current (a) 1 2 3 90 100 110 6 4645 f16 40 50 60 70 80 120 4 5 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 1 2 3 90 100 110 6 4645 f17 40 50 60 70 80 120 4 5 400lfm 200lfm 0lfm ambient temperature (c) 30 0 load current (a) 1 2 3 90 100 110 6 4645 f18 40 50 60 70 80 120 4 5 400lfm 200lfm 0lfm LTM4625 rev c
19 for more information www.analog.com applications information table 7. output voltage response vs component matrix ( refer to figure 20 ) c in part number value c out 1 part number value c out 2 part number value murata grm 21 br 61 e 106 ka 73 l 10 f , 25 v , 0805, x 5 r murata grm 21 br 60 j 476 me 15 47 f , 6.3 v , 0805, x 5 r sanyo 4 tpe 100 mzb 4 v 100 f taiyo yuden tmk 212 bbj 106 kg-t 10 f , 25 v , 0805, x 5 r taiyo yuden jmk 212 bj 476 mg-t 47 f , 6.3 v , 0805, x 5 r murata grm 31 cr 61 e 226 me 15 l 22 f , 25 v , 1206, x 5 r taiyo yuden tmk 316 bbj 226 ml-t 22 f , 25 v , 1206, x 5 r v out ( v ) c in ( ceramic ) ( f ) c in ( bulk ) c out 1 ( ceramic ) ( f ) c out 2 ( bulk ) ( f ) c ff ( pf ) v in ( v ) droop ( mv ) p-p derivation ( mv ) recovery time ( s ) load step ( a ) load step slew rate ( a / s ) r fb ( k ) 1 10 47 5, 12 5 72 40 1 1 90.9 1 10 100 10 5, 12 5 60 40 1 1 90.9 1 10 47 5, 12 5 127 40 2 1 90.9 1 10 100 10 5, 12 5 90 40 2 1 90.9 1.2 10 47 5, 12 5 76 40 1 1 60.4 1.2 10 100 10 5, 12 5 65 40 1 1 60.4 1.2 10 47 5, 12 5 145 40 2 1 60.4 1.2 10 100 10 5, 12 5 103 40 2 1 60.4 1.5 10 47 5, 12 5 80 40 1 1 40.2 1.5 10 100 10 5, 12 5 70 40 1 1 40.2 1.5 10 47 5, 12 5 161 40 2 1 40.2 1.5 10 100 10 5, 12 5 115 40 2 1 40.2 1.8 10 47 5, 12 5 95 40 1 1 30.1 1.8 10 100 10 5, 12 5 80 40 1 1 30.1 1.8 10 47 5, 12 5 177 40 2 1 30.1 1.8 10 100 10 5, 12 5 128 40 2 1 30.1 2.5 10 47 5, 12 5 125 40 1 1 19.1 2.5 10 100 10 5, 12 5 100 50 1 1 19.1 2.5 10 47 5, 12 5 225 40 2 1 19.1 2.5 10 100 10 5, 12 5 161 50 2 1 19.1 3.3 10 47 5, 12 5 155 40 1 1 13.3 3.3 10 100 10 5, 12 5 122 60 1 1 13.3 3.3 10 47 5, 12 5 285 40 2 1 13.3 3.3 10 100 10 5, 12 5 198 60 2 1 13.3 5 10 47 5, 12 5 220 40 1 1 8.25 5 10 47 5, 12 5 420 40 2 1 8.25 LTM4625 rev c
20 for more information www.analog.com applications information figure 19. recommended pcb layout safety considerations the ltm 4625 modules do not provide galvanic isolation from v in to v out . there is no internal fuse . if required , a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure . the device does support thermal shutdown and over current protection . layout checklist / example the high integration of ltm 4625 makes the pcb board layout very simple and easy . however , to optimize its electrical and thermal performance , some layout consid - erations are still necessary . ? use large pcb copper areas for high current paths , including v in , gnd and v out . it helps to minimize the pcb conduction loss and thermal stress . ? place high frequency ceramic input and output capaci - tors next to the v in , pgnd and v out pins to minimize high frequency noise . ? place a dedicated power ground layer underneath the unit . ? to minimize the via conduction loss and reduce module thermal stress , use multiple vias for interconnection between top layer and other power layers . ? do not put via directly on the pad , unless they are capped or plated over . ? use a separated sgnd ground copper area for com - ponents connected to signal pins . connect the sgnd to gnd underneath the unit . ? bring out test points on the signal pins for monitoring . ? keep separation between clkin , clkout and freq pin traces to minimize possibility of noise due to crosstalk between these signals . figure 19 gives a good example of the recommended layout . v in c out gnd v out r fb 4625 f19 gnd c in LTM4625 rev c
21 for more information www.analog.com applications information figure 20. 4 v in to 20 v in , 1.5 v output at 5 a design figure 21. 2.375 v in to 5 v in , 1 v at 5 a output design figure 22. 4 v in to 20 v in , tw o phases , 1.5 v at 10 a design v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin freq clkout v out 10f 25v 47f 6.3v v in 4v to 20v v out 1.5v 5a fb comp gnd 40.2k sgnd 4625 f20 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin clkout freq 5v v out 10f 25v 1f 6.3v 47f 6.3v v in 2.375v to 5v v out 1v 5a fb comp gnd 90.9k sgnd 4624 f21 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin 2mhz clock 162k clkout freq v out 10f 25v 47f 6.3v v in 4v to 20v v out 3.3v 5a fb comp gnd 13.3k sgnd 4624 f22 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin v out 10f 25v 2 47f 6.3v 2 20.1k v in 4v to 20v v out 1.5v 10a fb comp gnd 4625 f23 sgnd clkout freq 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin clkout freq v out fb comp gnd sgnd figure 23. 4 v in to 20 v in , 3.3 v output with 2 mhz external clock LTM4625 rev c
22 for more information www.analog.com figure 24. 4 v in to 20 v in , 1.2 v and 1.5 v with coincident tracking applications information v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin v out 10f 25v 2 47f 6.3v 47f 6.3v 60.4k v in 4v to 20v v out 1.5v 5a v out2 1.2v 5a fb 40.2k comp gnd 60.4k 60.4k 4625 f24 sgnd freq clkout 0.1f v in sv in run intv cc mode phmode track/ss pgood LTM4625 clkin v out fb comp gnd sgnd freq clkout LTM4625 rev c
23 for more information www.analog.com package description ltm 4625 component bga pinout package row and column labeling may vary among module products . review each package layout carefully . pin id function pin id function pin id function pin id function pin id function a 1 comp a 2 track / ss a 3 run a 4 freq a 5 clkin b 1 fb b 2 phmode b 3 gnd b 4 sgnd b 5 clkout c 1 v out c 2 pgood c 3 gnd c 4 mode c 5 sv in d 1 v out d 2 v out d 3 gnd d 4 gnd d 5 v in e 1 v out e 2 v out e 3 gnd e 4 intv cc e 5 v in LTM4625 rev c
24 for more information www.analog.com package description package top view 4 pin ?a1? corner y x aaa z aaa z detail a package bottom view 3 see notes suggested pcb layout top view 0.000 2.540 1.270 1.270 2.540 0.630 0.025 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 e d c b a 1 2 3 4 5 pin 1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature ?b (25 places) a detail b package side view m x y z ddd m z eee a2 d e e b f g detail a 0.3175 0.3175 bga 25 0517 rev c ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? bga package 25-lead (6.25mm 6.25mm 5.01mm) (reference ltc dwg # 05-08-1905 rev c) 6 see notes symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 6.25 6.25 1.27 5.08 5.08 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 total number of balls: 25 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht z detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! please refer to http :// www . linear . com / product / ltm 4625 # packaging for the most recent package drawings . LTM4625 rev c
25 for more information www.analog.com information furnished by analog devices is believed to be accurate and reliable . however , no responsibility is assumed by analog devices for its use , nor for any infringements of patents or other rights of third parties that may result from its use . specifications subject to change without notice . no license is granted by implication or otherwise under any patent or patent rights of analog devices . revision history rev date description page number a 08/15 added footnote 7 b 06/17 changed run pin absolute maximum rating from sv in to 22 v added pin 1 mark to pin configuration 2 c 04/18 corrected connection of phmode to intv cc /2 for 90 phase shift 10 LTM4625 rev c
26 for more information www.analog.com d16850-0-4/18(c) www.analog.com ? analog devices, inc. 2014-2018 related parts package photo part number description comments ltm 4624 lower current than ltm 4625 , lower v in , lower v out accuracy , same package bga footprint and height 4 a , 4 v < v in < 16 v maximum , 2% v out accuracy , does not have clock synchronization ltm 4623 ultrathin lga , lower current than ltm 4625 , same package footprint 1.82 mm height , 6.25 mm 6.25 mm lga , 3 a ltm 4619 dual 4 a 4.5 v < v in < 28 v maximum , 15 mm 15 mm 2.82 mm lga ltm 4644 quad 4 a configurable up to 16 a , 4 v < v in < 16 v maximum , 9 mm 15 mm 5.01 mm bga ltm 4649 10 a 4.5 v < v in < 18 v maximum , 9 mm 15 mm 4.92 mm bga ltm 8020 200 ma , higher v in than ltm 4625 , same package footprint 4 v < v in < 40 v maximum , 6.25 mm 6.25 mm 2.32 mm lga design resources subject description module design and manufacturing resources design : ? selector guides ? demo boards and gerber files ? free simulation tools manufacturing : ? quick start guide ? pcb design , assembly and manufacturing guidelines ? package and board level reliability module regulator products search 1. sort table of products by parameters and download the result as a spread sheet . 2. search using the quick power search parametric table . techclip videos quick videos detailing how to bench test electrical and thermal performance of module products . digital power system management analog devices family of digital power supply management ics are highly integrated solutions that offer essential functions , including power supply monitoring , supervision , margining and sequencing , and feature eeprom for storing user configurations and fault logging . LTM4625 rev c

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